Saved searches

Use saved searches to filter your results more quickly

Cancel Create saved search Sign up Reseting focus

You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session. You switched accounts on another tab or window. Reload to refresh your session.

Notifications You must be signed in to change notification settings

Ezhiloviya18/Direct-Mapped-Cache-Simulator

This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.

Go to file

Folders and files

Last commit message Last commit date

Latest commit

History

View all files

Repository files navigation

Direct Mapped Cache Simulator

Welcome to the Direct Mapped Cache Simulator project! This project demonstrates the simulation of a direct-mapped cache system using Python. It allows you to explore how cache hits and misses are managed based on the cache size, memory size, write policy, and more.

Table of Contents

Introduction

The Direct Mapped Cache Simulator project showcases the functionality of a direct-mapped cache system. This simulator enables you to understand how cache memory interacts with main memory when accessing memory addresses, and how cache hits and misses are handled.

Features

Usage

  1. Run the simulator script as mentioned in the installation instructions.
  2. Input cache size, memory size, write policy, write allocation policy, and offset bits.
  3. Input the number of memory addresses you want to simulate.
  4. Provide memory addresses one by one as prompted.
  5. Review the simulation results, including cache hits, misses, hit rate, and miss rate.

Technologies Used

Contributing

Contributions to enhance the project are welcome! Feel free to submit issues and pull requests. For significant changes, open an issue first to discuss potential improvements.